打印 上一主题 下一主题

[公司招聘] 台积电(中国)有限公司招募

  [复制链接]
跳转到指定楼层
楼主
3993 11 tsmcsh_hr 发表于 2016-3-9 11:20:35
Back-end ASIC designer/engineer

职位描述:
Responsibilities:
1. Be responsible for 16/10/7nm chip implementation for internal or customer projects.
2. Design methodology development and innovation for advanced technology challenges.
3. EDA tool enablement and customer’s support if necessary.

Key experience:
1. 3yrs above working experience, hands on experience on synthesis, automatic place and route, timing closure, design rule check or layout versus schematic
2. Experience with major design flows (Cadence Encounter/Innovus, Synopsys ICC(2))
3. Experience implementing large complicated digital circuits of 1M+ cells with macros
4. Experience with chip level partitioning including floorplaning and powerplaning.
5. Experience with integrating multiple blocks and macros and timing closure between blocks
6. Experience with designing under multiple power domains with UPF and/or CPF
7. Experience with designing high speed clock networks (eg. mesh, H-tree, etc.)
8. Good exposure to designing under advanced process nodes (40nm or below)
9. Good understanding of standard cell library kits (characterization, trouble-shooting)
10.Good understanding of timing closure algorithms and optimization strategies
11.Good scripting / programming skills (C/C++/C#, Java, Perl, Tcl, Python, etc.)

Personal Attributes:
1. Willing to take new challenge and work under dynamic environment
2. Self-motivated to pursue excellence and willing to take ownership
3. Team player who help team member achieving common goal

Qualifications:
Education: MS and above is preferred
Skills: programming, logic synthesis (Design Compiler/RTL Compiler/Genus), automatic place-and-route (Innovus/Encounter/ICC/ICC2), RC extraction (QRC/StarRC), timing sign-off (Tempus/PrimeTime), power sign-off (Voltus/Redhawk), design rule check / layout versus schematic (Calibre), low power design verification (MVRC/Conformal), library characterization (Liberate/Variety)

Language: English, Mandarin
职能类别:集成电路IC设计/应用工程师 版图设计工程师

Front-end designer/engineer

职位描述:
Key experience:
1. 4 yrs above working experience, Hands on experience on design, verification, synthesis, formal verification, timing closure.
2. Hands on experience in integrating complex SoC.
3. Hands on experience in designing IPs, memory controller, X-bar, CPU/GPU/DSP
4. Hands on experience of DFT and MBIST
5. Experience in architecture, micro-architecture evaluation.
6. Hands on experience in high speed design
7. Hands on experience in low power design
8. Hands on experience in building the verification environment and methodology from scratch.
9. Hands on experience in FPGA, emulation, UVM methodology.
10.Experience in full chip development cycle, from architecture to silicon bringup.

Personal Attributes:
1.Willing to take new challenge and work under dynamic env.
2.Willing to work under world class team to pursue excellence.
3.Team player.

Qualifications:
Education: MS and above is preferred
Skills: verilog, vhdl, system verilog, dc shell, primetime, vcs/ncsim, dftmax, tetramax, sms/tessent,
mvrc, upf, cpf,
uvm, fpga, emulation,
High level language programming.
Language: English, Mandarin
职能类别:集成电路IC设计/应用工程师 电子技术研发工程师
沙发
folkbassist 发表于 2016-3-10 13:40:44 来自手机
动力运行部,排气工程师,招不招
来自: 微社区
地板
wx_XmBWKKb8 发表于 2016-3-29 17:48:07 来自手机
应用物理学,学习过半导体基础知识,对半导体有深刻理解,希望给个机会
来自: 微社区
5#
漫天游云 发表于 2016-3-29 20:50:27 来自手机
特种气体工程师求职
来自: 微社区
6#
folkbassist 发表于 2016-4-5 20:36:47 来自手机
酸碱废气,VOCs,特气,真空,需要吗
来自: 微社区
7#
沫以沁泠 发表于 2016-5-17 21:26:03
主持楼主,顶一下
8#
zvdau 发表于 2016-5-17 23:19:38
看过,的确不错。谢谢楼主












厂家供应30V3.2A电源适配器
9#
YAMI 发表于 2016-5-19 10:51:32
半导体招聘求职   495833395
10#
chen1q 发表于 2016-5-21 18:10:46
你好!非常想到贵公司工作,与台积电一起进步,希望给我个机会谢谢
您需要登录后才可以回帖 登录 | 立即注册

本版积分规则

加入我们,

发现科技可以让生活更美好...

立即注册

如果您已拥有本站账户,则可

推荐阅读

��
中立 专业 诚实 善良

© 2009-2016

意见反馈:admin@211ic.com

官方客服微信:hr211ic

沪ICP备14040998号-1

社会化关��

新浪微博 | 知乎专栏

微信扫一扫关注我��
小黑屋|手机版|Archiver|广告联系|半导体技术天地| ( )  
返回顶部 返回列表